Non-linear pcm decoder



Jan. 30, 1968 MASAO KAWASHIMA ET AL NON-LINEAR PCM DECODER Filed Jan. 8, 1964 FIG! ZYl-f/g IQ man F,

CONJUGA TE SWITCH MEANS 2 Sheets-Sheet l FIG. 2 9

FIG. 4'

United States Patent OfiFice 3,366,947 Patented Jan. 30, 1968 3,366,947 NON-LINEAR PCM DECODER Masao Kawashima and Shigehiko Hinoshita, Yokohamashi, Japan, assignors to Fujitsu Limited, Kawasaki, Japan, a corporation of Japan Continuation-impart of application Ser. No. 253,231, Jan. 22, 1963. This application Jan. 8, 1964, Ser. No. 336,522

4 Claims. (Cl. 340--347) ABSTRACT OF THE DISCLOSURE Two groups of parallel-connected resistances have values in geometric order and form groups of parallel branches. Each branch of one group corresponds to a branch in the other and to a respective bit in a PCM code group. A circuit connects a pair of series resistors and the groups of parallel branches in series across a constant voltage source to form a voltage divider having an output terminal between the two groups of parallel branches. Switches are provided in each parallel branch. A seriesto-parallel PCM input oppositely switches both switches of each pair of switches in corresponding branches of each group of parallel branches depending upon the respective code values of the bit in a pulse-code-modulated group.

This is a continuation-in-part of our application Ser. No. 253,231, filed Jan. 22, 1963, and now abandoned.

Our invention relates to non-linear encoders and decoders for signal modulation in communication systems.

In a more particular aspect our invention relates to expanding digital-to-analog decoders for compressed pulse-code-modulated (PCM) signals in telephone transmission systems. In such systems a signal compressor at the sending end of the system provides non-linear compression coding, thereby reducing quantum noise that accompanies pulse-code-modulation and increasing the dynamic range of signal transmission, and an expander at the receiving side reestablishes the original linear transmission characteristic.

These compressors and expanders, or compandors, are usually composed of non-linear elements such as conventional diode pairs. However, compandors constructed as a resistance switching network would facilitate adjusting the operating characteristics of the signal compressor and expander, and would also improve the system stability against changes in temperature or other causes of unstable performance.

Thus it is an object of our invention to provide a nonlinear expanding decoder composed of resistance elements.

It is another object of this invention to provide a nonlinear expanding decoder using resistance switching networks and having symmetrical expansion characteristics.

Another object of the invention is to provide a compandor system wherein the selection of compression characteristics may be effected merely by changing the value of one element, for example a resistance.

Still another object of the invention is to provide a compandor circuit using simple and readily available parts and having simple reliable construction.

The various novel features of our invention are pointed out in the claims forming a part of this specification. Other objects and advantages of our invention will become obvious from the following detailed description when read in the light of the accompanying drawing, wherein:

FIG. 1 is a schematic diagram of a known non-linear, hyperbolic, decoding circuit;

FIG. 2 is a coordinate diagram of the input and output characteristics of the circuit in FIG. 1;

FIG. 3 is a block diagram of a non-linear decoding circuit according to the present invention;

FIG. 4 shows typical input-output characteristics curves of a decoding circuit of FIGS. 3 and 5;

FIG. 5 is a schematic circuit diagram of the non-linear decoding circuit embodying features of the invention and shown in FIG. 3; and

FIG. 6 is a block diagram of a non-linear coding circuit embodying features of the invention.

FIG. 1 illustrates a known digitalto-analog expanding decoder. Here a constant voltage E between a terminal (also designated E and ground connects directly to a plurality of resistors designated by their relative values Z R, 2* R R. Each of the resistors connects at its other end to respective resistors 2 KR, 2 KR KR. The junctions of these respective groups of resistors connect respectively to ground by virtue of respective switches S S S The last-mentioned group of resistors connect at their other ends to a terminal E representing the decoded and expanded output voltage E. The switches S S S are actuated respectively by the successive digits of a PCM coded input signal having 11 digits.

Each PCM code group of 11 digits has a value A out of a total value T which can be carried by 11 digits. Thus wherein A equals 0 or 1 and 05X 31. When the values A are 0, the corresponding switches S are on. When the values A are l, the switches S are off.

In FIG. 1 the expanded analog output Y=E/E Where OgYgl, has a value relative to X, and hence an inputoutput characteristic according to the following equation:

(m- 1)X YT mX 1 wherein m=R+l, (m 1) is a parameter representing the expansion determined by the circuit of FIG. 1. The characteristic is shown in FIG. 2. This characteristic only expands the values A and X as they increase.

However, a symmetrical expansion characteristic about a median value between 0 and T often is desired. One way to accomplish this would be to duplicate the circuit of FIG. 1 with another circuit of reversed polarity, or to change the polarity of the DC. power supply, or to use other means responsive to the input of where X=0 is at /2T and Our invention facilitates obtaining the required symmetrical expansion characteristic. As a feature of the invention, we operate respective switch pairs conjugately according to the respective digits in a PCM input code and indicate our output by a rational function, the denominator of which is a quadratic form of the input. De-

tails of the function are mentioned below with respect to FIGS. 3 and 5 which both illustrate an example of a circuit embodying features of the invention. FIG. 3 is a block diagram and FIG. 5 a detailed schematic of the same circuit.

In the present disclosure, operation of switches conjugately or conjugately switching is intended to be defined as opposite complementary switching. This may be illustrated by two groups of switches S S S and S S S of which the switches of the same subscript correspond to each other. When the switch S is ON, the switch S is OFF and vice versa. When the switch S is ON, the switch S is OFF and vice versa. When the switch S is ON, the switch S is OFF and vice versa. When the switch S is ON, the switch S is OFF and vice versa, and so on. The switches corresponding to each pair of switches thus operate in opposite complementary fashion.

In FIG. 5 a received quantized and compressed PCM input signal having 7 digits per code group passes from an input terminal I to a delay line or shift register R having 7 output taps t to r time-spaced from each other according to the digital spacing of the PCM code bits. The code bits of each group are thus made simultaneous at the output taps. Each tap connects to one input of respective AND gates A to A The input signal also passes to a clock device C which produces one set pulse for each code group (7 bits) in unison with the time that the last digit in each code group reaches the first tap t and the first AND gate A and hence in unison with the time that the respective binary digits in each code group reach their respective taps t to t (and gates A to A The set pulse opens the gates A to A for the duration of one digit and hence permits them to pass the respective now-simultaneous code bits to respective flip-flops FF to PR, which have been reset previously to one condition by another pulse from clock device C. Depending upon whether each digit (bit) of the code group is a mark or a space the flip-flops FF to FP will remain in that condition or flip over. The flipped-over ones of the flip-flops F-F to FF then render conductive the respective transistor switches S to S to those bases they are connected. The flip-flops which have remained in their reset condition due to presence of a space render conductive those transistor switches S to S to whose bases they are connected.

The emitter-collector paths of the transistors 8 to S each connect a respective resistor R to 2 R, having respective values of 100 ohms, 200 ohms, 400 ohms, 800 ohms, 1.6 kilohms, 3.2 kilohms, and 6.4 kilohrns, between a common +6-volt source E and a common 1.9 kilohrns resistor Rg. Similarly the emitter-collector paths of respective transistors S to S connect seven resistors R to 2 R, having respective values 100 ohms, 200 ohms, 400 ohms, 800 ohms, 1.6 kilohms, 3.2 kilohms, and 6.4 kilohms, between a common ground and a common 1.9 kilohms resistor Rg. The resistors Rg and Rg' connect together to form an output terminal E whose median voltage level is approximately 3 volts.

In operation, the sequential digits (bits) in the PCM code groups (series PCM) pass through the shift register which, together with clock device C, renders them simultaneous (parallel PCM) so that they now can simultaneously control seven flip-flops FP to FF These open or close the switches S to S and S to S conjugately so that a voltage divider is established between the 6- volt point E and ground, with a mid-point E and constituent resistances whose total values depend upon the code input. The flip-flops retain the output at E until the end of the next code group since without a new set pulse the signals from the shift register are unable to affect the respective conditions of flip-flops FF to FF Thus for each digital, binary, POM input value A, there exists an analog output value E symmetrically from a median output value E 2. Thus, if

A vn-l X=2 and 1:2 14,2

- group (OXl).

where :21 and n=number of digits in the code Now, in FIG. 3, if

1 Gr R2rr-1 R=1009, n=7, then 1 1 y+ E: l /\(r, v

1 1 R m A5 W 2" Nu,

Now if I E 1 2 l2 i -2Q 051 31 andm 1+ then ('m -1)X (m -X This characteristic is shown in FIG. 4. As seen from the above, the XY expansion characteristic varies while retaining its symmetry relative to a zero point according to the value of m, which is determined by circuit constants. This characteristic does not change basically for any given load connected to the output terminal E of FIG. 3, and only the output level and value m are adjusted thereby. The network can be utilized as a non-linear expanding decoder and a pair of such networks can be used eifectively for telephone PCM transmission devices as non-linear signal coder and decoder respectively, the former having a compression characteristic by using the network as a partial decoder of a feedback coder of the known type.

The circuit of FIG. 5 has a number of advantages compared to that of FIG. 1. First, the adjustment in actual use is simpler because the types of resistances are less. Secondly, in selecting the compression characteristics of FIG. 1 it is necessary to change the resistance R for each digit in order to change the value of Rg. However, in

'FiG. 3, only a change of Rg is necessary. T hirdly, symmetry is obtained with simple elements of the usual type such as flip-flops.

A compressor using .the expander circuit of FIG. 5 is shown by the block diagram of FIG. 6. There an amplifier AMP passes the amplified analog input signal to a linear PCM encoder LE of the known type. The decoder ED is the one shown in FIG. 5, and provides a negative feedback to the amplifier AMP.

It will be obvious to those skilled in the art that the invention may be embodied other than by the construction described in detail herein.

We claim:

1. An expanding pulse-code-modulation decoder comprising two groups of parallel-connected resistances having values in geometric order to form groups of parallel branches, each branch of one group correspondingto a branch in the other and to a respective bit in a PCM code group, a pair of series resistors, a constant-voltage source, circuit means connecting said resistors and said groups in series across said constant voltage source to form a voltage divider having an output terminal between said two groups, switch means in each parallel branch, and seriesto-parallel PCM input means for oppositely switching both switch means of each pair of switch means in corresponding branches of each group depending upon the respective code values of the bits in a pulse-code-modulated group.

2. An expanding pusle-code-modulation decoder comprising two groups of parallel-connected resistances having values in geometric order to form groups of parallel branches, each branch of one group corresponding to a branch in the other and to a respective bit in a PCM, code group, the values of each resistance being 2 Rwher,e

21:1, 2, 3 a pair of series resistors, a constantvoltage source, circuit means connecting said resistors and said groups in series across said constant voltage source to form a voltage divider having an output terminal between said two groups, switch means in each parallel branch, and series-to-parallel PCM input means for op positely switching both switch means of each pair of switch means in corresponding branches of each group depending upon the respective code values of the bits in a pulse-codemodulated group.

3. An expanding pulse-code-modulation decoder comprising two groups of parallel-connected resistances having values in geometric order to form groups of parallel branches, each branch of one group corresponding to a branch in the other and to a respective bit in a PCM code group, a pair of series resistors, a constant-voltage source, circuit means connecting said resistors and said groups in series across said constant voltage source to form a voltage divider having an output terminal between said two groups, switch means in each parallel branch, said circuit means connecting said resistor pair between said two groups and forming said output at the junction between said resistor pair, and series-to-parallel PCM input means for oppositely switching both switch means of each pair of switch means in corresponding branches of each group depending upon the respective code values of the bits in a pulse-code-modulated group.

4. An expanding pulse-code-modulation decoder comprising two groups of parallel-connected resistances having values in geometric order to form groups of parallel branches, each branch of one group corresponding to a branch in the other and to a respective bit in a PCM code group, a pair of series resistors, a constant-voltage source, circuit means connecting said resistors and said groups in series across said constant voltage source to form a voltage divider having an output terminal between said two groups, switch means in each parallel branch, PCM input means including shift register means for converting the successive PCM bits in each code group to simultaneous bits, and a plurality of flip-flop means each responding to respective bits in each group for oppositely switching the switch means in each corresponding branch pair.

References Cited UNITED STATES PATENTS 6/1959 Carbrey 32538 3,175,212 3/1965 Miller 325-38 X JOHN W. CALDWELL, Primary Examiner.

DAVID REDINBAUGH, Examiner.

J. T. STRATMAN, Assistant Examiner. 

